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83390078DDS
- DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器(LPF)。频率累加器对输入信号进行累加运算,产生频率控制数据X(frequency data或相位步进量)。相位累加器由N位全加器和N位累加寄存器级联而成,对代表频率的2进制码进行累加运算,是典型的反馈电路,产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器,以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works
Xilinx-FIR
- 基于Xilinx FPGA实现的系数可装载数字滤波器源代码-Configurable Digital Filter Based on FPGA (using Verilog under Matlab 2008a)
fir
- 数字电路设计中的,fir滤波器设计,我做的是8位宽的,利用vhdl实现,附带了完整的代码,报告,我没有对我的信息进行删除,是希望大家能够诚实的利用这个代码,提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information i
cic_dec_8_five
- CIC抽取滤波器,抽取系数8,verilog版本,用于数字下变频-CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion
DDS1
- 直接数字频率合成器(Direct Digital synthesizer)是从相位概念出发直接合成所需波形的一种频率合成技术。一个直接数字频率合成器由相位累加器、加法器、波形存储ROM、D/A转换器和低通滤波器(LPF)构成-Direct digital frequency synthesizer (Direct Digital synthesizer) is the concept of direct synthesis from the requirements phase of a wav
ddc_filter
- 基于数字下变频的低通滤波器设计,原理和设计理念-digital down convert or ddc low digital filter design
QPSKdigitalreceiver
- QPSK全数字接收机PDF,详细介绍了QPSK全数字接收机的构成,环路滤波器、内插器、Gardner定时恢复等部分的详细设计-QPSK digital receiver PDF, details of the composition of QPSK digital receiver, loop filter, interpolator, Gardner Timing Recovery and other parts of the detailed design
FPGA1IIR4
- 关于iir介绍,希望与大家共同提高。对于了解此滤波器的学习以及研究很有帮助,资料的详细功能-About iir introduction, hope we can together. Filter learning for understanding and study of this useful, detailed information on features
FIR_matlab_verilog
- matlab 仿真低通滤波器,然后用verilog硬件实现-using matlab to simulate a fir lowpass, then using verilog to implement it.
FIR_chanbing
- FIR滤波器的verilog HDL语言编写的,希望对大家有用-FIR filter verilog HDL languages, we hope to be useful
FIR2
- 以VERILOG语言描绘的用TLC549和TLC5615的数字低通滤波器的程序-VERILOG language used to describe the TLC549 and TLC5615 digital low pass filter process
86verilog
- 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字 滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了 对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结 果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求- W ith t
verilog
- 数字信号的处理,是用FPGA开发板实现的,可供做数字滤波器的提供参考-Digital signal processing is implemented with FPGA development board available for reference to do the digital filter
fir_lms
- verilog语言编写LMS(最小均方误差)自适应滤波器。-verilog language LMS (least mean square error) adaptive filter.
FIR_Filter
- verilog的32阶FIR低通滤波器描述-verilog 32-order FIR low-pass filter described
filter_40MHz
- 数字化中频接收机,用在AD之后的带通滤波器,VERILOG描述,32阶-Digital IF receiver, used in the AD after the bandpass filter, VERILOG descr iption, 32-step
Digital-Signal-Processing-with-FPGA
- FPGA结合DSP设计,如FIR、IIR滤波器,CORDIC算法,多重采样率信号处理,FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters,VHDL/Verilog code
IIR_filter
- 本实例利用硬件乘法器实现一个IIR滤波器。文件包含实现的verilog代码。-The example used to implement a hardware multiplier IIR filter. File contains the implementation of the verilog code.
digital-filter
- Verilog语言综合的固定频率的数字滤波器,用于滤除夹杂在固定频率信号上的杂波信号,包含了Quaetus工程和仿真文件。-Verilog language integrated fixed-frequency digital filter for filtering out mixed signals at a fixed frequency noise on the signal contains Quaetus engineering and simulation files.
cic.verilog
- 3阶的32倍抽取cic滤波器verilog代码-Level 3, 32 times the extraction of cic filter verilog code